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Optimizing Compilers for MIPS-based Products |
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The Green Hills Optimizing Compilers for MIPS-based architectures all utilize a common code generator with architecture-specific optimizations. Each supported MIPS architecture and processor has its own particular pipeline and instruction set characteristics. Supported features include:
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Processor Options - One option for each supported MIPS architecture and processor. This setting determines the instructions permitted, as well as the pipeline optimization strategy used.
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Position Independent Code (PIC) and Data (PID) - Allows code and data to be created which can be placed anywhere in memory and still run correctly.
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MIPS Assembler Compatible Output - Generate assembly language output which is compatible with native MIPS assemblers from MIPS-based workstations from Silicon Graphics and other companies.
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MIPS16e Instruction Set - Generate code for MIPS16e ASE.
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MIPS-3D ASE Support - The MIPS-3D ASE is supported through intrinsic functions.
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64-bit Integers - Supports 64-bit data types, constants, and expressions for all MIPS processors, including those with 32 bit registers.
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Far Function Calls - Handles code that exceeds the limits of the MIPS call instruction.
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Inline Prologue - Generates inlined code or calls a routine when saving and restoring registers.
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Small Data Area - The Green Hills Compilers collect frequently accessed variables into a block of up to 64KB of memory. This enables single instruction access to data within this block, saving code size and improving performance.
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Run-Time libraries |
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A complete implementation of the C, C++, EC++ and Ada 95 libraries are included in compiler distributions. Full featured start-up code and libraries include automatic copy of data from ROM to RAM and system call emulation. Source code to the run-time libraries is available so that users can customize routines according to the special needs of their applications.
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MIPS16E - MIPS16 |
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Green Hills C/C++ Optimizing Compilers provide user-selectable optimization options that trade-off code size vs. execution efficiency. In particular, for the MIPS16e and MIPS16 ASEs, benchmark tests have proven the effectiveness of the Green Hills Compilers in producing the smallest executable file for a given source program.
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CodeBalance |
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Green Hills Software offers CodeBalance,a powerful utility program that enables the user to make critical performance/code-size trade-offs. By analyzing the performance profile on a function by function basis, CodeBalance performs re-compilation in 16-bit mode starting with the functions that have the least effect on execution time. This achieves code-size reduction with minimal increase in execution time. Other compilers cannot perform function-specific 16-bit mode compilation, and must compile all functions in a file either in 16 or 32-bit mode. Green Hills Software offers the powerful #pragma-based capability to choose function-by-function, and a utility to automate this process based on a performance profile feedback, to enable optimized results.
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The MULTI Integrated Development Environment |
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MULTI provides a host-based (Windows 9x/NT/2000/ME/XP PC or UNIX workstation) graphical environment for MIPS target development. Host-target connectivity is provided through a variety of means, depending on the target environment. MULTI supports many MIPS-based evaluation boards. These boards can be accessed through a variety of interfaces:
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Bare Board Access (No RTOS or ROM Monitor) - MULTI supports on-chip debugging through JTAG (EJTAG) hardware through the MDI (MIPS Debug Interface) protocol. MIPS-based boards from MIPS Technologies, IDT, NEC, Philips, Toshiba and others are supported by the Green Hills Probe,EPI MAJIC,Macraigor OCD, Agilent Emulation Probe and First Silicon Solutions probe.
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ROM Monitor - MULTI supports LSI, NEC, IDT and Toshiba boards with YAMON,PMON and IDTsim.
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Commercial RTOS Support - MULTI supports MIPS boards running royalty-free INTEGRITY and ThreadX, both available from Green Hills Software, Tornado/VxWorks from Wind River Systems. MULTI provides multitask-aware debugging, and special commands that allow tasks to be stopped upon system events such as task creation.
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Custom RTOS Support - MULTI can be interfaced with a custom RTOS through integration of the Green Hills INDRT API. INDRT provides all the debug information needed by MULTI, and is easily integrated into user code.
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Instruction Set Simulators (ISS) - Instruction Set Simulators are used as host based software replacements for expensive hardware based targets. MULTI is tightly integrated with the simulators, providing the same full debug features that would be available with a hardware target: host I/O, command window, extended profiling and hardware breakpoints. The MIPSsim ISS, suitable for use with MIPS32 and MIPS64 cores from MIPS Technologies, is available as an Instruction Accurate (IA) model; an optional Cycle Accurate (CA) model is also available. Simmips, suitable for all MIPS-based chips, is provided as an Instruction Accurate model. Both Simmips and MIPSsim simulate target CPU cache for those processors which support it.
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